1. Field of the Invention
The present invention generally relates to semiconductor devices and a method of manufacturing the same, and more particularly, a semiconductor device formed on an SOI (Silicon on Insulator) substrate in order to implement high speed operation and a method of manufacturing the same.
2. Description of the Background Art
Referring to FIGS. 75 to 77, description will be given of a plan structure and a sectional structure of a semiconductor device having a gate array, having a plurality of gates disposed thereon, formed on a silicon substrate.
At a prescribed position of a silicon substrate 316, formed is a field oxide film 302. Silicon substrate 316 includes a p type MOS field effect transistor forming region 310, and an n type MOS field effect transistor forming region 312 formed therein. Gate electrode 304 are disposed regularly in respective MOS field effect transistor forming regions 310, 312. In a semiconductor device including a gate array structure as described above, respective blocks in which gate electrodes 304 are disposed are electrically isolated from each other by field oxide film 302. In one block, active regions are electrically isolated by gate electrode 304.
Referring to FIG. 78, the operational principle of isolation of transistors by an electrode will be specifically described, taking n type MOS field effect transistor forming region 312 as an example. By fixing gate electrode 304 to a ground potential, for example, a transistor 317 formed of a gate electrode 318, a source region 320 and a drain region 322, and a transistor 323 formed of a gate electrode 324, a source region 326 and a drain region 328 are electrically isolated from each other. These transistors can operate independently. In p type MOS field effect transistor forming region 310, by fixing to the power supply potential gate electrode 304 between transistors to be isolated, the similar effects can be obtained.
As described above, a method for electrically isolating transistors by fixing a gate electrode between the transistors to be isolated to the power supply potential or the ground potential is called a gate isolation method. The gate electrode between the transistors is called a gate isolation gate electrode. The gate isolation method is suitable for high integration as compared to an isolation method using a field oxide film, because the gate electrode can effectively be used in the former method.
Description will now be given of a semiconductor device configuring a 3-input NAND gate using the above-described gate isolation method with reference to FIGS. 79 and 80. FIG. 80 is a plan view of the semiconductor device configuring a 3-input NAND gate shown in (a), (b) of FIG. 79. In FIG. 80, the upper block corresponds to a p type MOS field effect transistor forming region, and the lower block corresponds to an n type MOS field effect transistor forming region. By configuring a gate electrode and a source/drain region in an internal interconnection structure as shown in FIG. 80, a 3-input NAND gate can be easily configured. In FIG. 80, by fixing the rightmost gate electrode of the p type MOS field effect transistor forming region and the rightmost gate electrode of the n type MOS field effect transistor forming region to the power supply potential and the ground potential, respectively, these forming regions can be electrically isolated from the other adjacent transistors.
A semiconductor device having a conventional gate array having a plurality of gates disposed therein, which is described above, is formed on a bulk silicon substrate. Formation of such a semiconductor device on an SOI (Silicon on Insulator) substrate is currently studied. If a CMOS (Complementary Metal-Oxide Semiconductor) field effect transistor is formed on an SOI substrate, the following features can be obtained as compared to a CMOS field effect transistor formed on a bulk silicon substrate:
(1) Increase in drivability
(2) Reduction of junction capacitance in source/drain region
(3) Latchup free
FIGS. 81 and 82 show cross sections in the case where MOS field effect transistors are formed on a bulk silicon substrate and an SOT substrate, respectively. In the case of the transistor fabricated on the SOI substrate, a depletion layer under a channel extends only to a buried oxide film. Therefore, a voltage applied to a gate electrode effectively generates carriers in the channel, resulting in increase of drivability. Since a source/drain junction is formed only in a surface perpendicular to an SOI layer because of the buried oxide film, the junction capacitance in the source/drain region can be reduced. Since respective MOS field effect transistors are electrically isolated completely by the buried oxide film, latchup, which has been conventionally problematic, will not occur.
Because of the above features, high speed operation without latchup can be expected by forming a gate array on an SOI substrate.
In an MOS field effect transistor fabricated on the conventional SOI substrate, the breakdown voltage between source and drain is lowered as compared to an MOS field effect transistor fabricated on the bulk silicon substrate, because of the substrate floating effect of an SOI layer serving as a channel. Referring to FIGS. 83 and 84, described is how the breakdown voltage between source and drain is lowered because of the substrate floating effect. FIG. 83 shows the Id-Vd characteristics of an MOS field effect transistor fabricated on a bulk silicon substrate, and FIG. 84 shows the Id-Vd characteristics of an MOS field effect transistor fabricated on an SOI substrate.
Referring to these figures, in the MOS field effect transistor fabricated on the bulk silicon substrate, the breakdown voltage is 5V or more. On the other hand, in the MOS field effect transistor fabricated on the SOI substrate, the breakdown voltage is only approximately 2V.
Description will now be given of the substrate floating effect with reference to FIGS. 85 and 86. A hole 338 generated by impact ionization in a depletion layer in the vicinity of a drain region 334 is stored in a lower portion of a channel region 332 in the vicinity of a source region 330. Holes 338 are sequentially accumulated in the lower portion of channel region 332, thereby increasing the potential of an SOI layer to induce injection of an electron 336 from source region 330. The injected electron 336 reaches the vicinity of drain region 334 to generate new hole 338. As described above, a so-called feed forward loop formed by injection of electron 336 and generation of hole 338 causes the breakdown voltage between source and drain to decrease.
In order to prevent the substrate floating effect, several methods are being studied. The most reliable one is a method of preventing storage of holes 338 by fixing the potential of a channel region 344, with reference to FIG. 87. In the case of an n type MOS field effect transistor, for example, storage of holes 338 can be prevented by fixing the potential of the channel region to ground potential. Similarly, in the case of a p type MOS field effect transistor, storage of holes 338 can be prevented by fixing the potential of the channel region to power supply potential. In order to fix the potential of channel region 332, the SOI layer under gate electrode 304 is drawn out, and a region 350 for providing a body contact 352 is formed. As a result, storage of holes 338 can be prevented. However, this method necessitates an additional region 350 for forming a body contact, which hampers high integration of a semiconductor device.
One object of the present invention is to provide a semiconductor device preventing reduction of a breakdown voltage between source and drain, which has been a problem to an MOS field effect transistor formed on a conventional SOI substrate, and a method of manufacturing the same.
Another object of the present invention is to provide a semiconductor device using an SOI substrate which can be highly integrated by disposing efficiently a region of a body contact, and a method of manufacturing the same.
In order to achieve the above-described objects, the semiconductor device according to the present invention includes, in one aspect, a semiconductor layer, a first transistor forming region, a second transistor forming region, and a third field oxide film. The semiconductor layer is formed on the main surface of an insulating layer. The first transistor forming region includes a plurality of MOS field effect transistors of a first conductivity type formed on the main surface of the semiconductor layer, and first field oxide films respectively isolating the plurality of MOS field effect transistors of the first conductivity type.
The second transistor formation region includes a plurality of MOS field effect transistors of a second conductivity type, and second field oxide films respectively isolating the plurality of MOS field effect transistors of the second conductivity type. The third field oxide film is formed to cover the main surface of the semiconductor layer and to reach the main surface of the insulating layer. The third field oxide film is provided for isolating the first transistor forming region and the second transistor forming region.
In order to achieve the above objects, the semiconductor device according to the present invention includes, in another aspect, a semiconductor layer, a first transistor forming region, a second transistor forming region, and a field oxide film. The semiconductor layer is formed on the main surface of an insulating layer. The first transistor forming region is formed on the main surface of the semiconductor layer and includes a plurality of MOS field effect transistors of a first conductivity type, and first field shield gate electrodes respectively isolating the plurality of MOS field effect transistors of the first conductivity type.
The second transistor forming region is formed on the main surface of the semiconductor layer and includes a plurality of MOS field effect transistors of a second conductivity type, and second field shield gate electrodes respectively isolating the plurality of MOS field effect transistors of the second conductivity type. The field oxide film is formed to cover the main surface of the semiconductor layer and to reach the main surface of the insulating layer. The field oxide film is provided for isolating the first transistor forming region and the second transistor forming region.
According to the semiconductor device, the field oxide film is formed to cover the main surface of the semiconductor layer and to reach the main surface of the insulating layer. As a result, the first transistor forming region and the second transistor forming region can be electrically isolated from each other completely. Therefore, latchup between the first transistor forming region and the second transistor forming region can be prevented completely.
In order to achieve the above objects, the semiconductor device according to the present invention includes, in a still another aspect, a semiconductor layer, a first transistor forming region, a second transistor forming region, and a mesa isolation region. The semiconductor layer is formed on the main surface of an insulating layer. The first transistor forming region is formed on the main surface of the semiconductor layer and includes a plurality of MOS field effect transistors of a first conductivity type, and first field shield gate electrodes respectively isolating the plurality of MOS field effect transistors of the first conductivity type.
The second transistor forming region is formed on the main surface of the semiconductor layer and includes a plurality of MOS field effect transistors of a second conductivity type, and second field shield gate electrodes respectively isolating the plurality of MOS field effect transistors of the second conductivity type. The mesa isolation region is provided for isolating the first transistor forming region and the second transistor forming region.
According to the semiconductor device, the mesa isolation region is provided for isolating the first transistor forming region and the second transistor forming region. As a result, the first transistor forming region and the second transistor forming region can be electrically isolated from each other completely. Therefore, latchup between the regions can be prevented completely.
In order to achieve the above objects, the method of manufacturing a semiconductor device according to the present invention includes, in one aspect, the following steps.
First, an insulating layer is formed on a substrate. A semiconductor layer is then formed on the insulating layer. An oxide film is formed on the semiconductor layer. A plurality of first field oxide films reaching the insulating film are formed in a prescribed position with an LOCOS (Local Oxidation Of Silicon) method. Again with the LOCOS method, second field oxide films smaller in thickness than the first field oxide films are formed in a region sandwiched by the first field oxide films.
In order to achieve the above objects, the method of manufacturing a semiconductor device according to the present invention includes, in another aspect, the following steps.
First, an insulating film is formed on a substrate. A semiconductor layer is then formed on the insulating film. An oxide film is formed on the semiconductor layer. First field oxide films having a first width and second field oxide films having a second width smaller than the first width are formed with an LOCOS method. Again with the LOCOS method, only the first field oxide films are further oxidized in order to increase in thickness until they reach the insulating film.
In order to achieve the above objects, the method of manufacturing a semiconductor device according to the present invention includes, in a still another aspect, the following steps.
First, an insulating film is formed on a substrate. A semiconductor layer is then formed on the insulating film. An oxide film is formed on the semiconductor layer. A nitride film is formed on the oxide film. A resist film having a prescribed pattern is formed on the nitride film. With the resist film used as a mask, the semiconductor layer is etched to a prescribed depth, forming recessed portions of a prescribed depth in the semiconductor layer.
After removing the resist film, a resist film having a prescribed pattern is again formed. With this resist film used as a mask, the nitride film positioned between the recessed portions is patterned. After removing the resist film, with the nitride film used as a mask, first field oxide films obtained by growth of the oxide film in the recessed portion reaching the insulating film, and second field oxide films between the recessed portions are formed with an LOCOS method.
In order to achieve the above objects, the method of manufacturing a semiconductor device according to the present invention includes, in a further aspect, the following steps.
First, an insulating film is formed on a substrate. A semiconductor layer is then formed on the insulating film. An oxide film is formed on the semiconductor layer. A buffer layer is formed on the oxide film. A nitride film is formed on the buffer layer. On the nitride film, formed is a first resist film having a first opening portion and a second opening portion larger in width than the first opening portion. With the resist film used as a mask, the nitride film is etched until the surface of the buffer layer is exposed.
A second resist film is formed so as to fill only the first opening portion. With the first resist film and the second resist film used as a mask, the buffer layer is etched. After removing the first and second resist films, with the nitride film used as a mask, first field oxide films reaching the insulating film and second field oxide films are formed at positions of the first opening portion and the second opening portion, respectively, with an LOCOS method.
According to the method of manufacturing a semiconductor device, it is possible to easily form a third field oxide film provided to cover the main surface of the semiconductor layer and to reach the main surface of the insulating layer for electrically isolating the first transistor forming region and the second transistor forming region completely, first field oxide films in the first transistor forming region, and second field oxide films in the second transistor forming region.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.